More and more integrated circuits are equipped with built-in self-test devices, also called BIST devices. Such devices are often used in the test phase in the production of integrated circuits. They are designed to assist the test equipment in testing specific functionalities and to reduce the testing time.
Use of a binary multiplier is frequently needed in a BIST device. FIG. 1 shows a multiplication calculation methodology used as a basis for many binary multiplier structures. The aim is to multiply, for example, a binary number A of 4 bits A0 to A3, by a binary number B of four bits B0 to B3. All the partial products or terms AiBj, sixteen terms in the example, are divided into 7 columns, such that each term AiBj is arranged in the column of rank i+j. The ranks of the columns correspond to the weights of the result R of the multiplication.
The result R is obtained by adding the binary numbers formed by the juxtaposed terms of the columns. A column is completed by a 0 when there is no term. The result thus comprises 7 bits R0 to R6 corresponding respectively to the columns, and an additional most significant bit R7 receiving any carry digit of the addition.
Many multiplier structures, which favor calculation speed, such as the Dadda multiplier or Wallace tree multiplier, are designed to perform the operations shown in FIG. 1 in parallel using combinatory logic. The number of logic gates of these structures increases with the square number of the number of bits of the multiplicands. It may be undesirable to sacrifice this area of silicon for an element that does not require a nearly immediate calculation result, as is the case in most built-in test systems.